The present invention relates to an FET (field effect transistor) memory device in which a plurality of trap-type (e.g., MNOS or MONOS-type) nonvolatile memories are arranged in matrix form.
In conventional memory devices of this type, a substrate (well) is common to all memory cells. Therefore, simply selecting the gate of a certain memory transistor will cause the other memory transistors connected to the same line to be selected as well. To avoid this, a write-inhibition voltage is applied to bit lines of memory transistors not to be selected. Further, in order to prevent a current leakage from the bit lines, transistors for cell selection are provided in addition to the memory transistors.
FIGS. 5 and 6 are circuit diagrams showing conventional memory devices of the above type. The device of FIG. 5 is disclosed in Japanese Patent Application Unexamined Publication No. Sho. 62-45182, and the device of FIG. 6 in Japanese Patent Application Unexamined Publication No. Sho. 59-211281. In FIG. 5, reference numeral 30 designates a well which is common to all memory cells M1, M2, M3, M4, etc. Each memory cell has a transistor Q.sub.s for cell selection besides a memory transistor Q.sub.m. Also in FIG. 6, as can be understood from the fact that portions 31, 32 of each of memory cells M1-M3 are connected to each other, a single common well is employed in this device. Each memory cell includes a memory transistor 33 and a transistor 34 for cell selection.
As described above, since in conventional matrix-type memory devices each memory cell requires a transistor for cell selection besides a memory transistor, its size is increased as much, which results in a large-sized memory device. Further, additional wiring for and control voltage application to the transistors for cell selection make the construction of the memory device more complicated.